Semiconductor memory devices, that is, semiconductor components with at least one memory cell, are used to store data in digital systems. In correspondence with the type of data storage and the various ways in which the data can be written and read-out again, these semiconductor memory devices are divided into various categories. If the memory device continues to store the information even after the supply voltage has been turned off, the device is a non-volatile memory (read-only memory), such as a ROM device. The category of volatile memory devices includes static and dynamic memories such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory). After production, data can be freely written to and read from these volatile memory components. In contrast, data cannot usually be written to the non-volatile memory components after they have been produced, and they are therefore used essentially only as sources from which data can be read.
Read-only memories (ROM's) are used in digital systems to store constants, control data, and program instructions. The information is stored by providing transistors at the intersections between the word lines and the bit lines to connect the word lines to the bit lines or by not providing any transistors there so as not to connect the two types of lines. These MOS (Metal Oxide Semiconductor) transistors are arranged in the form of a matrix in a memory field region of the ROM component.
The cells for a MOS-ROM component (Metal Oxide Semiconductor Read-Only-Memory) require only one transistor to store a bit. In one possible design, namely, that of an n-channel transistor, the source region is connected to ground (“low potential”). To store a bit (“high” or “low” potential), an electrical contact is placed in the drain region of the transistor to establish an electrical connection between the transistor and the bit line (BL). When the word line (WL), which represents the gate of the transistor, is now opened, “low potential” can flow from the source region to the drain region and can be read via the bit line. As a result, the 1-bit ROM memory cell is programmed to the logical state “O”. To program the “high potential”, the electrical contact between the drain region of the transistor and the bit line is omitted. The bit line is therefore undefined, and the 1-bit ROM memory cell is programmed to the other logical state “1”.
In accordance with the complexity of the system, the memory requirement can range from only a few bits to many billions of bits. If relatively little memory is required, the memory devices are integrated as modules into a chip along with the data paths and control logic. If it is necessary to store large amounts of data, standardized units are produced. The criteria under which standard memory units are evaluated are cost (and thus complexity), speed of access to the data, power loss, and reliability.
Read-only memories or ROM components differ with respect to whether the data are written into them by electrical pulses during the production process or after production. The ROM components considered within the scope of the state of the art, in which the data are written into the devices during production, are called “mask-programmable ROM components”. Depending on the method used to encode the data during production, mask-programmable ROM's can be either of the diffusion type, of the contact type, or of the via-contact type.
For ROM's of the diffusion type, programming is carried out by forming or omitting transistors at the intersections between the word lines and the bit lines in correspondence with the data to be stored. The encoding or programming therefore takes place at a very early stage of the production process. For this type of ROM, many additional process steps are required after programming to finish the memory component, and as a result the “turn-around-times” are long. The turn-around-time is the time the customer must wait for delivery of the finished product after he has provided the manufacturer with his specifications for the desired mask-programmable ROM.
In ROM's of the contact type, the memory cells are programmed by creating or leaving out the electrical contacts between the memory cell transistors and the bit lines located in the first metallization plane above the memory cell transistors. In the via-contact type, the programming is shifted to a higher metallization plane. Because of the different arrangements of the word lines and bit lines required in the via-contact and contact types, however, the amount of surface area required is greater than that for the diffusion type. The data in these memory components known as “mask-programmable ROM's” cannot be erased or overwritten.
In the case of mask-programmable ROM's, it is especially desirable to minimize the so-called “turn-around-time” (TAT) or “cycle time”. Efforts are always being made to reduce this turn-around-time. At the same time, it is desirable to minimize the amount of space required by the memory cells.
A mask-programmable ROM component is disclosed in U.S. Pat. No. 5,959,877, in which the programming can be carried out in the second, third, or a higher metallization plane. The transistors are arranged in the form of a matrix in the memory cell field, thus forming rows and columns. The transistors arranged in one row are connected to the same word line. The transistors arranged in adjacent columns are connected by their gate terminals to different word lines. Only the diffusion regions of the two outer transistors of a column, i.e., the diffusion regions facing the edge of the memory cell field, are connected to ground potential. All of the other diffusion regions, each of which is assigned to two transistors, can be contacted by the bit lines situated above them. The transistors are therefore connected in series between the potentials of the word lines, and the diffusion regions of adjacent transistors are connected to several potential nodes. Although it is true that the cycle time can be kept relatively short by shifting the programming into a higher metallization plane, this wiring design requires a very large amount of space to accommodate the complicated configuration and layout of the word lines and bit lines.
In the case of mask-programmable ROM cell fields, word lines are usually produced out of polysilicon. Because polysilicon lines have a high resistance value, it is advantageous to amplify the signals on these polysilicon lines or to adjust them to the required signal strength by means of an additional line in one of the metallization layers, especially when the memory cell field has a very large number of memory cells and it is therefore impossible to avoid a drop in the potential along the transistors connected to one word line.
An arrangement of lines of this type for row selection and potential equalization is shown in FIG. 1. FIG. 1 shows two memory cell transistors, which are arranged next to each other in a column of a memory cell field. The first memory cell has a first memory cell transistor, the gate G1 of which is connected to a first word line W1. Via its drain terminal D1, this first memory cell transistor is contacted by a bit line BL, i.e., programmed to the first state, by way of a contact K, a first contact path P1 in a first metallization plane, a first via connection V1, a second contact path P2 in a second metallization plane, and a second via connection V2. A source region 50 is assigned to the first and to the second memory cell transistor. The second memory cell transistor is designed in the same way as the first memory cell transistor. The separating lines TL designate the boundaries of a memory cell and characterize the unit cell.
To equalize the mass potential, to which the source region 50 is connected, a ground potential equalization line PAM is provided, with which the source region 50 can be brought into contact. For row-select/potential-equalization, each memory cell has its own electrical row-select/potential-equalization line PAW1 or PAW2, where the two row-select/potential-equalization lines PAW1 and PAW2 are formed in a metallization plane above the bit line BL. These row-select/potential equalization lines PAW1 and PAW2 are therefore produced only after the memory cells have been programmed, which has the effect of prolonging not only the process of producing the mask-programmable ROM's but also the overall cycle time.